Acronyms used in the present disclosure include RF: Radio Frequency; IF: Intermediate Frequency; and ADC: Analog to Digital Converter. Implementation of an RF/IF/ADC receiver chain into an integrated CMOS device is subject to non-linear signal distortion that impairs the ability to correctly recover and decode a desired signal in the presence of undesired signals (non-linearities). As is known in the art, post-compensation of signal distortion, using digital signal processing (DSP), can be used in designing and implementing a highly linear receiver.
FIG. 1 shows an example of prior art RF receiver chain used to receive wireless signals. A signal received at an antenna 50 is amplified using a low noise amplifier (LNA) 52, and then filtered by a filter, for example, a band pass filter 54, to remove harmonic distortion products caused by the non-linearity of the LNA 52. The filtered signal output of the BPF 54 is converted to a lower frequency or intermediate frequency (IF) using a mixer 56 that receives the output of the BPF 54 and the output of a local oscillator (LO) 58. The frequency of the IF (output of mixer 56) is equal to the difference between the frequency of the LO 58 and the frequency of the signal output from the BPF 54. As is known in the art, a mixer such as the mixer 56 works by exploiting the non-linearity of the mixer 56. As such, the IF signal output from the mixer 56 contains harmonic distortions that are to be removed, typically through filtering, by using, for example, a low pass filter 60.
Intermodulation distortion occurring at the same IF frequency as the signal cannot be removed by filtering and can be cause for concern. As the signal received at the antenna 50 is processed by the LNA 52, the BPF 54, the mixer 56, and the LPF 60, the amplitude of the signal diminishes. A programmable or variable gain amplifier (VGA) 62 can be used to boost the signal power; however, the VGA 62 typically introduces harmonic and intermodulation distortion. In many receivers a surface acoustic wave (SAW) filter 64 can be used to tightly filter the signal band of interest. Not only will the SAW filter 64 remove much of the harmonic distortion, it will also remove a significant amount of intermodulation distortion that falls outside the SAW filter bandwidth. Optionally, a second VGA 63 can be positioned to receive the output of the SAW filter 64, and to provide an amplified signal to the ADC 66. Those knowledgeable in the art will appreciate that intermodulation distortion will remain in-band and that it is not possible to remove this through simple filtering.
The ADC 66 samples the output to the VGA 63 and converts this output into digital samples using an Analog-to-Digital-Converter (ADC) 66. Within the ADC 66, non-linearities often exist that impair the signal output from the ADC. As an additional concern, any signal component, desired or otherwise, that lies outside the Nyquist sampling band will be aliased back into the desired band and impair the signal at the output of the ADC 66. Further, the ADC 66 includes a sample and hold (S/H) circuit (not shown). The input bandwidth of the ADC is often many times higher than that of the IF. As such, many orders of distortion can be incurred in the S/H circuit. Also, due to circuit specifics, the non-linearity of the ADC 66 may be modified by a high-pass memory process. That is, there are substantially no distortion products at low frequency due to the S/H circuit. However, due to the S/H circuit operation, signal content above 50% of the S/H clocking rate aliases down below this rate. This is the typical ADC aliasing process known to those knowledgeable in the art.
FIG. 2 shows a representative view of non-linearities incurred in the receiver chain of FIG. 1 up to, but not including, the S/H circuit of the ADC 66. In FIG. 2, it is assumed that the received signal occupies the entire signal channel bandwidth. In FIG. 2, the signal “X” 70 represents the analytic form of the signal (complex signal with no negative frequency component). Of note, the signal “X” 70 is idealized in that it has infinitely sharp roll-off in frequency and is flat across frequency. In practice, this will likely not be the case; however there is no loss of generality in using the “square-shape” signal “X” 70. Finally, the lower frequency portion of each of the signals is labeled “L” while the higher frequency portion of the signal is labeled “H”. The labeling is important for clarity when ADC sample aliasing is introduced.
The distortion products up to the third order are shown in FIG. 2. In this particular example, the different distortion products overlap in frequency, but this is not necessarily the case.
In FIG. 2, the second order intermodulation distortion product is identified as “|X|2” 72 as this is the numerical model to generate these terms. “|X|2” 72 can also be referred to as IM2. The IM2 terms from the VGA 63, which can be optional, will typically have little memory (i.e., will not depend significantly on frequency); however the IM2 terms from the front of the circuitry of the ADC 66 may have a high pass memory effect, hence the shape (slope) of “|X|2” 72. For example, the front of the circuitry of the ADC 66 may included buffering circuitry that is part of a sample and hold circuitry.
The third order intermodulation product is identified as “|X|2·X” 74 and can be referred to as IM3. Contributions to the IM3 term come from all parts of the receiver chain shown at FIG. 1. Prior to the ADC 66, the IM3 contribution will have little dependence on frequency (i.e., they will have little memory); however the IM3 term from the front of the circuitry of the ADC 66 will have a high pass memory effect, hence the shape (slope) of “|X|2·X” 74 shown at FIG. 2.
The second order harmonic distortion product is identified as “X·X” 76 and can be referred to as HD2. Depending on the cutoff frequency of a LPF 65 that can be placed after the second VGA 63, there could be a LPF memory effect (frequency dependence of HD2); however, the portion due to the front of the ADC circuit will have a high pass memory effect.
The third order harmonic distortion product is identified as “X·X·X” 78 and can be referred to as HD3. Depending on the cutoff frequency of the LPF after the second VGA 63, these could have a LPF memory effect, however, the portion due to the front of the ADC circuit will have a high pass memory effect.
In reality, the memory effects imposed on the HD2 and HD3 terms will be a combination of low pass from the LPF 60 and high pass due to the nature of the circuitry of the ADC 66. The low pass response of the LPF 65 placed after the second VGA 63 but before the ADC 66, is shown in FIG. 2, at reference numeral 80, and the high pass response of the ADC is shown at reference numeral 82. As further shown at FIG. 2, the high pass response 82 of the ADC 66 non-linearity is less dependent on frequency as the frequency increases. This is expected from the front circuitry of the ADC 66.
FIG. 3A is similar to FIG. 2; however the abscissa (x-axis) of FIG. 3A is now shown in units of sampling frequency fsamp. In the example of FIG. 3A, the signal “X” 70 lies in the second Nyquist zone. That is, “X” 70 is at a frequency that lies between 0.5* fsamp and fsamp. Thus, the frequency of the signal “X” 70 lies above the Nyquist aliasing frequency 0.5*fsamp. All signal components existing at the point of the S/H circuitry of the ADC 66 will alias into the first Nyquist zone. The signals in the odd order Nyquist zones will alias into the first Nyquist zone without frequency inversion, while those signals in the even order Nyquist zones, including the signal “X” 70, will alias into the first Nyquist zone with an inversion in frequency. This effect is shown in FIG. 3B. The use of the “L” (low frequency) and “H” (high frequency) labels is to help visualize the zone-folding for each of the signals. In FIG. 3B, the portions of the various signals shown in stippled lines is further folded into the second Nyquist zone.
Further, integration of an RF/IF/ADC receiver chain in CMOS devices is desirable as the integration allows for smaller footprint and reduced power consumption. Unfortunately, implementation of an RF/IF/ADC receiver chain in CMOS is subject to non-linearities, for example, as those described above, that will impair the ability to correctly recover and decode a desired signal in the presence of a larger signals.
FIG. 4 shows an example of performance requirement of a receiver, which is based on: 3GPP TS 45.005, “3rd Generation Partnership Project; Technical Specification Group GSM/EDGE Radio Access Network; Radio transmission and reception”, Release 10. The receiver is designed as a wide-band multicarrier receiver. In the presence of two strong signals having −43 dBm power each (referred to here as “jammer signals”), it must be possible to recover a weak desired signal (having −101 dBm power) with a signal to noise and distortion ration (SNDR) exceeding 10 dB. Due to receiver non-linearity, intermodulation and/or harmonic distortion, and ADC sample aliasing, distortion products from the jammer signals may fall within the desired signal bandwidth. Combined with other impairments such as thermal and ADC quantization noise, this can degrade the SNDR of the desired signal to less than the required 10 dB.
When the sampled signal contains a desired signal component that has lower than required SNDR the signal needs to be processed to improve the SNDR to acceptable levels. In the intended application, it is sufficient to reduce the distortion products that lie in the bandwidth of the signal of interest. Signal distortion products that lie outside this bandwidth (but still within the bandwidth of the wideband receiver) are not of concern as they can be removed by a downstream process through simple numerical filtering. A number of Digital Signal Processing (DSP) techniques are available to perform this task of in-band signal distortion removal, but they are typically very complex and power consuming. The challenge is to design a method to decrease distortion with sufficient improvement in SNDR without excessive power consumption.
Therefore improvements in the compensation of signal distortions are desirable.